A decoder, particularly row decoders, need to be able to provide an enabling signal of high current at the power supply voltage because of the capacitance of the relatively long line it must enable. One technique is to use a zero threshold transistor as a drive device. When a word line is to be selected, a zero threshold transistor is enabled by a signal at the amplitude of power supply voltage. Because of the near zero threshold voltage of a zero threshold transistor, the enabled transistor can provide an output at the amplitude of the power supply voltage. Such a technique is described in U.S. Pat. No. 4,264,828, Perlegos, et al.
Zero threshold transistors are not always available, however, due to the desire to minimize process complexity. For N-channel technology one technique is for all of the transistors to be doped to zero threshold and masking the transistors which are to be zero threshold voltage from the subsequent doping steps for the depletion and enhancement transistors. In the absence of zero threshold transistors, the initial doping of all the transistors can be for enhancement transistors so that only one subsequent doping step is required to obtain depletion transistors. The process for obtaining just enhancement and depletion transistors is simpler resulting in less expense and higher yields.
With the constraint that zero threshold transistors are not available, generating a signal at the amplitude of the power supply voltage for enabling a word line is more complicated. For dynamic random access memories (DRAMs) a technique for precharging a decoder prior to selection has been used. Such a technique is described in U.S. Pat. No. 4,087,044, Hofmann. This is useful in DRAMs when there is enough time prior to selection to precharge but not too much time so as to lose charge through leakage.
In static random access memories (SRAMs) and some other memories there is not an opportunity to precharge. For SRAMs, methods of bootstrapping have been developed. The problem with bootstrap techniques is that they normally use more power, particularly in the deselected decoders. For example, a memory may have 128 word lines each having a row decoder. When a word line is selected, 127 word lines are deselected. Consequently, the most power is likely to be lost in the deselected decoders. But since any one of the deselected decoders may be selected next, each deselected decoder must be ready to switch to the selected state. This state of readiness on the part of the deselected decoders normally causes a waste of power.